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Chris's Project Page - RISE summer 2004 |
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Intern: Christopher Picardo, University Notre Dame
Mentors: Ryan Castner and Tim Sherwood
Faculty Supervisors: Ryan Kastner and Tim Sherwood
Department: ECE and Computer Science |
QUANTIFYING RECONFIGURABLE COMPUTING SYSTEMS
In this paper we first provide a detailed description of common constraints
present on modern FPGAs (i.e. memory size and distribution, chip architecture,
bus width, broken components, etc.) Secondly, we show how to overcome these
problems by means of trade-offs, which can help maintain or improve performance
that allows the realization of robust computing systems. To achieve this goal
we design a video game system on a NIOS II development board from Altera
Corporation. Because the NIOS II board has at least one programmable
microprocessor, a master clock, programmable memory, a JTAG programmer, I/O
pins, standard expansion slots, and debugging tools like push buttons, switches
and LED displays, our system architecture (i.e. video game system architecture)
uses these FPGA components to design a RISC microprocessor, a data-path and
controller, data memory, address memory, video memory, and input and output
that connects to a VGA port and a game-pad controller. The goal is to make
these components achieve system level integration. Furthermore, since the
majority of image processing applications run faster on FPGAs than on
general-purpose processors, it is our intention to use the development of this
video game system as a learning tool where we can identify constraints,
quantify resources and find solutions to problems that appear during design and
implementation. The end result is a robust computing system.
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